1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a miniaturized semiconductor device capable of remarkably improving production efficiency and a method of fabricating the same.
2. Description of the Prior Art
FIG. 95 is a sectional block diagram showing an exemplary conventional semiconductor device. A semiconductor chip 101a formed on a wafer is mounted on a die pad 105b of a lead frame. Electrode pads 103 of the semiconductor chip 101a are connected with external leads 105a serving as external connecting terminals by wires 102. The wires 102 form wire connecting terminals 102b on portions con connected with the electrode pads 103, while forming wire connecting terminals 102a on portions connected with the external leads 105a. Portions excluding external terminals of the external leads 105a are sealed with insulating resin 104, as shown in FIG. 95.
FIGS. 96 to 100 show a method of fabricating the aforementioned semiconductor device. As shown in FIG. 96, a plurality of semiconductor circuit areas (semiconductor chip regions) 101a are arranged and formed on the wafer 101, for providing the electrode pads 103 on the surface of each semiconductor chip 101a. As shown in FIG. 97, the wafer 101 is cut in units of the semiconductor chip regions 101a, for obtaining each fragmented semiconductor chip 101a. Thereafter the fragmented semiconductor chip 101a is fixed to the die pad 105b of the lead frame, as shown in FIG. 98. Then, the electrode pads 103 arranged on the upper surface of the semiconductor chip 101a and the external leads 105 a are connected with each other by the wires 102, as shown in FIG. 99. Thereafter the portions excluding the terminals of the external leads 105a are sealed with the resin 104, as shown in FIG. 100. Finally, portions of the external leads 105a exposed from the sealing resin 104 are bent inward for reducing the size, thereby fabricating the semiconductor device shown in FIG. 95.
A semiconductor device such as a DRAM (dynamic random access memory), for example, having excellent reliability can be obtained by the aforementioned fabrication method.
However, the aforementioned semiconductor device employs the lead frame, and hence the external leads 105a are inevitably located outside the semiconductor chip 101a in a planar view. In order to eliminate such a factor inhibiting the semiconductor device from miniaturization, some proposals have heretofore been made. For example, FIG. 101 shows a structure proposed in Japanese Patent Laying-Open No. 9-162348 (1997). Referring to FIG. 101, resin projections 104a covered with metal films 115a are provided on the bottom of a semiconductor chip 101a for connecting the metal films 115a with electrode pads 103 of the semiconductor chip 101a with wires 102. According to this structure, no terminals for external connection are provided outside sealing resin, and hence this semiconductor device can be miniaturized.
FIG. 102 shows another structure proposed in Japanese Patent Laying-Open No. 10-98133 (1998). Referring to FIG. 102, external connection means 125a is arranged in proximity to a semiconductor chip 101a without employing a lead frame. In this semiconductor device, the semiconductor chip 101a and the external connection means 125a are sealed with resin 104 and exposed on the back surface. This semiconductor device can also be miniaturized due to the external connection means 125a located inside the sealing resin 104 in a planar view.
However, the structure according to Japanese Patent Laying-Open No. 9-162348 shown in FIG. 101 requires pattern formation for the metal films 115a covering the resin projections 104a. Therefore, the number of fabrication steps is complicatedly increased. Thus, the fabrication cost is increased, and the yield may be reduced.
In the structure according to Japanese Patent Laying-Open No. 10-98133 shown in FIG. 102, an additional member, i.e., the external connection means 125a must be arranged during fabrication steps. Therefore, the fabrication steps are complicated to increase the fabrication cost, and the yield may be reduced.
In addition, each of the aforementioned semiconductor devices is generally fabricated by cutting a wafer provided with semiconductor chips through prescribed processing steps along sections of the wafer for obtaining fragmented individual semiconductor chips. According to a general fabrication method, each of the semiconductor devices shown in FIGS. 96 to 100 is fabricated through a step of fragmenting the semiconductor chip in advance of a step of sealing portions of the wafer with resin.
When electrode pads of the semiconductor chip and connecting terminals are wire-bonded and sealed with resin through the step of fragmenting the semiconductor chip, alignment etc. must be performed in each fragmented semiconductor chip, leading to limitation of the production efficiency. While the price of a semiconductor device is reduced by mass production for facilitating popularization of the semiconductor device, the aforementioned system fabricating a semiconductor package for each fragmented semiconductor chip is problematic in view of mass productivity.
In the aforementioned method fabricating the semiconductor package for each fragmented semiconductor device, it is difficult to handle the semiconductor device when the same is miniaturized. It is obviously difficult to handle the aforementioned semiconductor device shown in FIG. 101 or 102 when the same is miniaturized.
Further, complicated processing steps are required for fabricating a semiconductor device such as the aforementioned miniaturized semiconductor device shown in FIG. 101 or 102 by stacking a plurality of individual fragmented semiconductor chips, and the finished semiconductor device is also complicated in structure. FIG. 103 shows a multilayer structure employing a lead frame. Referring to FIG. 103, the sizes of stacked semiconductor chips 101a must be gradually reduced in ascending order, and hence the number of stackable layers of the semiconductor chips 101a is limited. FIG. 104 shows a multilayer structure formed by stacking semiconductor chips 101a of the same size. It is understood from FIG. 104 that the semiconductor chips 101a of the same size must be stacked through a spacer 111. When the spacer 111 is employed, not only the structure is complicated but also a connecting step is required for each layer. Therefore, fabrication efficiency is disadvantageously reduced.